I. Field of the Disclosure
The field of the disclosure relates to dual-string digital-to-analog converters (DACs), and particularly to interconnections and switching of primary and secondary voltage dividers provided therein.
II. Background
A digital-to-analog converter (DAC) is a device that converts digital codes to representative analog signals. For example, the converted analog signals may be recreations of native analog signals previously converted into the digital codes by an analog-to-digital converter (ADC). A common use of ADCs and DACs is converting audio and video signals used in media devices (e.g. televisions, cell phones, MP3 players, etc.) from analog sign representations to digital signal representations, or vice versa.
One type of DAC is a dual-string DAC. A dual resistor string DAC (also referred to as “dual-string DAC”) requires fewer resistors and switches to convert digital codes into analog signal representations as compared to single resistor string DACs. A dual-string DAC includes a first resistor string that generates a coarse conversion of a digital code. A second resistor string of the dual-string DAC generates a finer interpolation of the coarse conversion of the digital code received from the first resistor string to provide an output voltage providing an analog signal representation of the digital code. For example, if a dual-string DAC is configured to convert six (6) bit binary digital codes into sixty-four (64) unique conversions (i.e., 26 conversions), each resistor string of the dual-string DAC could each include eight (8) resistors for a total of sixteen (16) resistors, as opposed to providing sixty-four (64) resistors in a single-string DAC.
For example, FIG. 1 illustrates an exemplary dual-string DAC 10 (referred to herein as “DAC 10”). The DAC 10 functions by applying a received input voltage Vin across a primary voltage divider circuit 12, referred to herein as “primary voltage divider 12.” The primary voltage divider 12 provides coarse voltage (i.e., analog signal) values by dividing the input voltage Vin across a plurality of primary resistors R(0)-R(N−1) in a primary resistor string 14 at selected resistor node pairs Nr(0)-Nr(N) at nodes between the primary resistors R(0)-R(N−1). For example, if N equals sixteen (16), this means the number of primary resistors R(0)-R(N−1) provided in the primary voltage divider 12 totals sixteen (16). In this example, the primary voltage divider 12 provides sixteen (16) unique divided primary voltages selectable by four (4) binary bits of a digital code provided to the primary voltage divider 12 for conversion. For example, the bits of a digital DAC input code 15 (hereinafter “DAC input code 15”) are used to select the primary voltages, as illustrated in FIG. 1. In this example, the most significant bits N of the DAC input code 15 are used to select the primary voltages. A coarse divided primary voltage value is selected by a primary switch unit 16 that selects a pair of primary switches U(0)-U(2N−1) to select a selected resistor node pair N, among a plurality of selected resistor node pairs Nr(0) to Nr(N) in the primary resistor string 14 to select one of the divided primary voltages as a selected coarse divided primary voltage Vp. This selected coarse divided primary voltage Vp is applied across a secondary voltage divider circuit 18, referred to herein as “secondary voltage divider 18.”
With continuing reference to FIG. 1, the secondary voltage divider 18 is provided in the DAC 10 and configured to further divide the selected coarse divided primary voltage Vp into a plurality of finer secondary voltages. In this regard, the secondary voltage divider 18 comprises a plurality of secondary resistors Rs(0)-Rs(Y−1) to form a secondary resistor string 20. Similar to the primary resistor string 14, the secondary resistor string 20 divides the applied primary voltage from the primary voltage divider 12 into finer, interpolated secondary voltages. As the primary voltage is applied across the secondary resistor string 20, a secondary output voltage Vout is selected by a secondary voltage divider switch 22. For example, if Y equals thirty-two (32), meaning the number of secondary resistors Rs(0)-Rs(Y−1) provided in the secondary voltage divider 18 totals thirty-two (32), the secondary voltage divider 18 provides thirty-two (32) unique divided secondary voltages. The thirty-two (32) unique divided secondary voltages are selectable by five (5) binary digital code bits provided to the secondary voltage divider 18. For example, the bits of the DAC input code 15 used to select the secondary voltages may comprise the least significant five (5) bits (LSB) of the DAC input code 15. A finer, interpolated secondary voltage value is selected by the secondary voltage divider switch 22 by selecting a resistor node Nsr. The selected resistor node Nsr is selected from among resistor nodes Nsr(0)-Nsr(Y) in the secondary resistor string 20 to provide a final, secondary output voltage Vout representing the converted DAC input code 15.
When the selected coarse divided primary voltage Vp is applied across the secondary resistor string 20 of the secondary voltage divider 18 in the DAC 10 in FIG. 1, the selected primary resistors R(0)-R(N−1) are placed in parallel to the secondary resistor string 20. The parallel placement of the selected primary resistors R(0)-R(N−1) with the secondary resistor string 20 would normally alter the effective resistive characteristics of the selected primary resistors R(0)-R(N−1). The effect of the altered effective resistive characteristics adjusts the selected coarse divided primary voltage Vp thereby providing an incorrect selected coarse divided primary voltage Vp to the secondary resistor string 20 for the DAC input code 15. To prevent the secondary resistor string 20 from altering the selected coarse divided primary voltage Vp across the selected primary resistors R(0)-R(N−1), isolation circuits VF1, VF2 are provided.
With continuing reference to FIG. 1, the isolation circuits VF1, VF2 are disposed between the primary resistor string 14 and the secondary resistor string 20. In this example, the isolation circuits VF1, VF2 are operational amplifiers. The operational amplifiers VF1, VF2 are each configured in a voltage follower mode to maintain the selected coarse divided primary voltage Vp applied to the secondary resistor string 20 in this example. The operational amplifiers VF1, VF2 maintain the ideal voltage across the secondary resistor string 20 by isolating the current flow of the primary voltage divider 12 from the secondary voltage divider 18. The effect of isolating the primary voltage divider 12 from the secondary voltage divider 18 is to preserve the native resistive characteristics of the primary voltage divider 12, thus maintaining a predictable, linear voltage division on the primary voltage divider 12 and the secondary voltage divider 18 of the DAC 10. However, providing the operational amplifiers VF1, VF2 comes at the expense of an increase in area usage, consumption of power, and slower performance because the operational amplifiers VF1, VF2 require a settling time.